1. Introduction
The present invention relates to an apparatus to assist in the verification of software in a computer system.
2. Field of the Invention
It has long been appreciated that the most important objective when developing software is that of ensuring that the software is free of faults when released on the market. Studies have shown that the costs involved in eliminating software faults during initial development and testing is of the order of 0.1% of the cost of eliminating faults when software is in use by a purchaser.
Heretofore, the most common approach to eliminating faults in software during development has been to manually input test instructions and to monitor the corresponding output. This approach has been used because the complexity of much software does not lend itself to the automatic generation of test instructions and the manual approach allows a large degree of versatility. The major disadvantages of manual verification are that it is extremely time-consuming, especially for regression testing where there are revision up-dates in the software, as is often the case. Indeed, it is envisaged that if each revision up-date is to be tested satisfactorily, many man-days of skilled time are required. A further disadvantage of manual verification is that it is generally error prone as it is necessary for a person to visually monitor output over a long period of time.
In the past, some attempts at automating software verification have been directed towards specific aspects of software verification. For example, United Kingdom Patent Specification No. 2,096,371 A describes an apparatus for assisting in fault-finding in a data processing system. This apparatus appears to be useful in the testing of software loaded in a specific microprocessor and indeed, it has been designed with microprocessor time frames in mind. This prior apparatus is, however, not suitable for use with software loaded in other than a microprocessor and does not appear to have the required flexibility for regression testing.
Other attempts at automating software verification are software based and have the capability to simulate target software inputs and capture corresponding outputs. The testing software is generally run alongside the target software in the target computer. Accordingly, the target software is not tested in a similar environment to that in which it would normally be used. A further disadvantage of such testing systems is that they are usually only suitable for one type of target software language and operating system generally, and are thus not versatile.